1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and particularly to a row address decode circuit for a semiconductor memory circuit.
2. Description of the Related Art
FIG. 9 is a circuit diagram of a memory cell. The memory cell has an NMOS transistor 1, a capacitor 2, a word line WLi, and a bit line BLj. As the semiconductor memory circuit has many memory cells, a plurality of word lines WLi(i=1,2,3 . . .) and bit lines BLj are disposed in a matrix pattern. One of the word lines is selected and raised to a predetermined potential during each xe2x80x9cdata readxe2x80x9d or xe2x80x9cdata writexe2x80x9d operation.
To check the reliability of the semiconductor memory circuit, a wafer burn-in test is performed. During the wafer burn-in test, all of the word lines are raised to the predetermined potential at the same time to shorten the time needed to carry out the test.
FIG. 10 is a circuit diagram of a row address decode circuit 1000 which performs the wafer burn-in test, and FIG. 11 is an operational waveform diagram of the same. This row address decode circuit has a pre-decode circuit 10, a decode circuit 20, and a word driver circuit 30.
The pre-decode circuit 10 has parallel inverters 110xcx9c11n, NAND gates 120xcx9c12n, and NAND gates 130xcx9c13n. Address signals AX0xcx9cAXk, Inverted address signals AX0bxcx9cAXkb, are inputted to the NAND gates 120-12n. Wafer burn-in signal WBI is inputted to the inverters 110xcx9c11n. The output signals of the NAND gates 120-12n and the inverters 110-11n are respectively inputted to the NAND gates 130-13. This pre-decode circuit 10 outputs pre-decodes signal PAX0xcx9cPAXn of (n+1) bits. Half of k+1 is n+1 in this circuit.
The least significant address signal AX0 or AX0b, which is the inverted signal of AX0, is inputted to one input terminal of the NAND gate 120, and second to least significant address signal AX1 or AX1b, which is the inverted signal of AX1, is inputted to another input terminal of NAND gate 120. The third to least significant address signal AX2 or AX2b, which is the inverted signal of AX2, is inputted to one input terminal of the NAND gate 121, and fourth to least significant address signal AX3 or AX3b, which is the inverted signal of AX3, is inputted to another input terminal of NAND gate 121. Input signals are applied to all other NAND gates 122-12n in the same manner as described above. The NAND gates 120xcx9c12n output a logic xe2x80x9cLxe2x80x9d level only when both input signals are a logic xe2x80x9cHxe2x80x9d level.
When the wafer burn in signal WBI is L level (ground potential), which designates a disable state, the memory circuit operates in a normal mode. Nodes NI0xcx9cNIn are an H level (power supply potential). Therefore, the output signals of NAND gates 130xcx9c13n depend on the output signals of NAND gates 120xcx9c12n. NAND gates 130xcx9c13n output a logic L level when the output signal of NAND gates 120xcx9c12n is a logic H level.
When the wafer burn in signal WBI is an H level, which designates an enable state, the memory circuit operates in a burn-in test mode. Nodes NI0xcx9cNIn are L level. Therefore, all of the NAND gates 130xcx9c13n output a logic H level.
Decode circuit 20 has a P channel MOS transistor 21, an N channel MOS transistors 220xcx9c22n, and an inverter 23. Pre-decode signals PAX0xcx9cPAXn and a reset signal PREb are inputted to the decode circuit 20. The reset signal PREb become an L level when the decode circuit 20 is reset, and the reset signal PREb become an H level when the decode circuit 20 is in an enable state. NMOS transistors 220xcx9c22n are connected in series. The source of 22n is connected to the ground level. The drain of the NMOS transistor 220 is connected to the node ND0. Pre-decode signals PAX0xcx9cPAXn are inputted to the gates of transistor 220xcx9c22n, respectively. The source of PMOS transistor 21 is connected to the power supply potential, and the drain is connected to the node ND0. The reset signal PREb is inputted to the gate of PMOS transistor 21. The node ND0 is connected to the input terminal of the inverter 23. The inverter 23 outputs a decode signal D0.
When the decode circuit is reset, reset signal PREb and all of the address signals AX0xcx9cAXn become an L level. Therefore, pre-decode signals PAX xcx9cPAXn become an L level. PMOS transistor 21 is in an on state, and the NMOS transistors 220xcx9c22n are in off state 20 in this case. The node ND0 becomes an H level, and the decode signal D0 becomes an L level.
When the decode line is activated, reset signal PREb becomes an H level. The PMOS transistor 21 is in an off state in this case. Address signals AX0xcx9cAXk are inputted to the pre-decode circuit 10. Pre-decode circuit 10 outputs pre-decode signals PAX0xcx9cPAXn. If all of the pre-decode signals PAX0xcx9cPAXn are an H level, all of the NMOS transistor 220xcx9c22n are in an on state. Therefore, the node ND0 becomes an L level, and the decode signal D0 becomes an H level. If one of the pre-decode signals PAX0xcx9cPAXn is an L level, one of the NMOS transistor 220xcx9c22n is in an off state. Therefore, the node ND0 keeps an H level.
When the wafer burn in test is performed, all of the pre-decode signals PAX0xcx9cPAXn become an H level. Therefore, the decode signal D0 is an H level during the wafer burn in test.
The word driver circuit 30 has an inverter 31, level shift circuit 32, PMOS transistor 33, and NMOS transistor 34. The level shift circuit changes the amplitude of the input signal. The input signal has an amplitude between the power supply potential and the ground potential. However, to activate a word line, a slightly high level than power supply potential is needed. This level is called the word line activate potential. Therefore, the level shift circuit is needed. The output terminal of the level shift circuit is connected to the gates of PMOS transistor 33 and NMOS transistor 34. The source of PMOS transistor 33 is connected to the word line activate potential. The source of the NMOS transistor is connected to the ground potential. The drains of transistors 33 and 34 are connected to a word line WLi.
When the decode signal D0 is an L level, the word driver circuit makes the word line WLi the ground potential. When the decode signal D0 is an H level, the word driver circuit makes the word line WLi word line an activate potential.
FIG. 10 shows one row address decode circuit. A memory circuit has a plurality of row address decode circuits. For example, address signals inputted to NAND gate 120 have four patterns. The first pattern is that the inputted signals are AX0 and AX1. The second pattern is that the inputted signals are AX0b and AX1. The third pattern is that the inputted signals are AX0 and AX1b. The fourth pattern is that the inputted signals are AX0b and AX1b. The same relationship applies to other NAND gates 121-12n. Therefore, there are 4(n+1) units of row address decode circuits and word lines in a memory circuit.
In the prior art, only the selected word line is activated during the normal mode, and all of the word lines are activated during the wafer burn-in test mode.
While the wafer burn in test is performed, there is not any electrical potential difference between the word lines. However, in the normal operation, there are electrical potential differences between the word lines. Therefore, the wafer burn-in test in the prior art can not test for the stress between word lines.
An object of the present invention is to provide a semiconductor memory device which allows stress acceleration testing between word lines.
A memory circuit includes a plurality of word lines connected to a plurality of memory cells and a plurality of row address decode circuits which selectively activate the plurality of word lines, respectively, and each having at least one address input terminal, a first terminal which receives a first wafer burn-in signal, and a terminal which receives a second wafer burn-in signal.
wherein the row address decode circuits activate all of the word lines when the first wafer burn-in signal and the second wafer burn-in signal are in an enable state, wherein the row address decode circuits activate a subset of the word lines when the second wafer burn-in signal is enable state and the first wafer burn-in signal is in a disable state.